Hey Reachy - Wake word detection - Impulses

Experiments

Name	Input	DSP Blocks	Learn Blocks	f32_V_Acc	f32_T_Acc	i8_V_Acc	i8_T_Acc	f32_Latency	f32_Flash	i8_Latency	i8_Flash
Experiment 1	1,500ms. @ 16000Hz	Audio (MFCC)	Classifier	97.6%	97.1%	97.4%	97.0%	5 ms.	160.2K	5 ms.	67.3K	View impulse
Experiment 2	1,500ms. @ 16000Hz	MFCC	Classifier	98.2%	97.2%	98.2%	-	6 ms.	65.6K	6 ms.	42.0K	View impulse
Experiment 3	1,500ms. @ 16000Hz	MFCC	Classifier	98.3%	97.0%	98.3%	97.1%	5 ms.	38.6K	5 ms.	34.4K	View impulse
Experiment 4	1,500ms. @ 16000Hz	MFCC	Classifier	97.3%	96.4%	97.3%	-	6 ms.	39.0K	6 ms.	34.5K	View impulse
Experiment 5	2,000ms. @ 24000Hz	MFCC	Classifier	96.9%	96.4%	96.9%	96.4%	7 ms.	54.8K	8 ms.	48.3K	View impulse
mfcc-conv2d-5f7	2,000ms. @ 16000Hz	Audio (MFCC)	Classifier	-	-	-	-	-	-	-	-	View impulse

Impulse information

Tags - Impulse tags

Source - Impulse source (Manual vs EON Tuner)

Created by - The user who originally created this impulse

Key metrics

f32_V_Acc - Accuracy (float32, validation set)

f32_T_Acc - Accuracy (float32, test set)

i8_V_Acc - Accuracy (int8, validation set)

i8_T_Acc - Accuracy (int8, test set)

f32_Latency - float32 Latency for the complete impulse.

f32_Flash - float32 Flash for the complete impulse.

i8_Latency - int8 Latency for the complete impulse.

i8_Flash - int8 Flash for the complete impulse.

Input block config

Win_Size - Window size

Win_Incr - Window increase

Freq - Frequency

Zero_Pad - Zero pad data

Processing block config

Norm - Normalization

Noc - Mel Frequency Cepstral Coefficients > Number of coefficients (Processing Block #1)

Fra_len - Mel Frequency Cepstral Coefficients > Frame length (Processing Block #1)

Fra_str - Mel Frequency Cepstral Coefficients > Frame stride (Processing Block #1)

Fil_num - Mel Frequency Cepstral Coefficients > Filter number (Processing Block #1)

FFT_len - Mel Frequency Cepstral Coefficients > FFT length (Processing Block #1)

Nws - Mel Frequency Cepstral Coefficients > Normalization window size (Processing Block #1)

Low_fre - Mel Frequency Cepstral Coefficients > Low frequency (Processing Block #1)

Hig_fre - Mel Frequency Cepstral Coefficients > High frequency (Processing Block #1)

Coe - Pre-emphasis > Coefficient (Processing Block #1)

Learn block config

Model - ML Model architecture (Learn Block #1)

Tc - Training cycles (Learn Block #1)

Lr - Learning rate (Learn Block #1)

Lo - Use learned optimizer? (Learn Block #1)

Bs - Batch size (Learn Block #1)

Acw - Auto-weight classes (Learn Block #1)

Data_Aug - Data augmentation (Learn Block #1)

Val_Size - Validation set size (Learn Block #1)

Val_Key - Split train/validation set on metadata key (Learn Block #1)

Mode - Visual / expert mode (Learn Block #1)

Thr_Mcr - Minimum confidence rating (Learn Block #1)

Accuracy metrics

f32_V_AUC - float32 Area under ROC Curve (validation set)

f32_V_WA_P - float32 Weighted average Precision (validation set)

f32_V_WA_R - float32 Weighted average Recall (validation set)

f32_V_WA_F1 - float32 Weighted average F1 score (validation set)

f32_T_AUC - float32 Area under ROC Curve (test set)

f32_T_WA_P - float32 Weighted average Precision (test set)

f32_T_WA_R - float32 Weighted average Recall (test set)

f32_T_WA_F1 - float32 Weighted average F1 score (test set)

i8_V_AUC - int8 Area under ROC Curve (validation set)

i8_V_WA_P - int8 Weighted average Precision (validation set)

i8_V_WA_R - int8 Weighted average Recall (validation set)

i8_V_WA_F1 - int8 Weighted average F1 score (validation set)

i8_T_AUC - int8 Area under ROC Curve (test set)

i8_T_WA_P - int8 Weighted average Precision (test set)

i8_T_WA_R - int8 Weighted average Recall (test set)

i8_T_WA_F1 - int8 Weighted average F1 score (test set)

Post-processing block config

No columns

Target device

Define your target device requirements to inform model optimizations and performance calculations. No device yet? Use the default settings which you can change at any time.

Target device

Processor family

Clock rate

| MHz

Max

Custom device name

Application budget

Specify the available RAM and ROM for the model's operation, along with the maximum allowed latency for your specific application. Not sure yet? Start with the defaults and modify them later on.

RAM

| KB

Max

ROM

| KB

Max

Latency

| ms

Max

Experiments

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

mfcc-conv2d-5f7