License Plate Detection - Impulses

Experiments

Name	Input	DSP Blocks	Learn Blocks	f32_V_Acc	f32_T_Acc	i8_V_Acc	i8_T_Acc	f32_Latency	f32_RAM	f32_Flash	i8_Latency	i8_RAM	i8_Flash
350 epoch TAO MBv2 0.25 SSD	160×160	Image	NVIDIA TAO SSD	52.1%	24.7%	49.1%	-	6468 ms.	2.4M	2.3M	4 ms.	726.0K	690.2K	View impulse
Image data #1 (Not cleaned dataset), Image, NVIDIA TAO RetinaNet #1 (Primary)	160×160	Image	NVIDIA TAO RetinaNet	70.2%	69.1%	65.6%	-	270535 ms.	1.2M	21.2M	120 ms.	755.8K	5.5M	View impulse
Image data #1 (Not cleaned dataset), Image, NVIDIA TAO RetinaNet #2 (200 epochs)	160×160	Image	NVIDIA TAO RetinaNet	76.3%	79.4%	73.0%	-	268835 ms.	1.2M	21.2M	125 ms.	755.8K	5.5M	View impulse
Image data #1 (Not cleaned dataset), Image, NVIDIA TAO RetinaNet #3 (350 epochs TAO MBv2 0.25 RetinaNet)	160×160	Image	NVIDIA TAO RetinaNet	80.6%	82.5%	77.3%	-	273169 ms.	1.2M	21.2M	129 ms.	755.8K	5.5M	View impulse
MBv2 RetinaNet TAO 160x160	160×160	Image	NVIDIA TAO RetinaNet	83.0%	85.6%	74.9%	-	171354 ms.	1.2M	21.2M	137 ms.	755.8K	5.5M	View impulse

Impulse information

Tags - Impulse tags

Source - Impulse source (Manual vs EON Tuner)

Created by - The user who originally created this impulse

Key metrics

f32_V_Acc - Accuracy (float32, validation set)

f32_T_Acc - Accuracy (float32, test set)

i8_V_Acc - Accuracy (int8, validation set)

i8_T_Acc - Accuracy (int8, test set)

f32_Latency - float32 Latency for the complete impulse.

f32_RAM - float32 RAM for the complete impulse.

f32_Flash - float32 Flash for the complete impulse.

i8_Latency - int8 Latency for the complete impulse.

i8_RAM - int8 RAM for the complete impulse.

i8_Flash - int8 Flash for the complete impulse.

Input block config

Img_Height - Image height

Img_Width - Image width

Resize_Mode - Resize mode

Processing block config

Norm - Normalization

Col_dep - Image > Color depth (Processing Block #1)

Learn block config

Model - ML Model architecture (Learn Block #1)

Bac - Backbone (Learn Block #1)

Notc - Number of training cycles (Learn Block #1)

Mlr - Minimum learning rate (Learn Block #1)

Mlr_MlrLB1 - Maximum learning rate (Learn Block #1)

Sof_sta - Soft start (Learn Block #1)

Ann - Annealing (Learn Block #1)

Qat - Quantization aware training (Learn Block #1)

IoU_thr - IoU threshold (Learn Block #1)

Con_thr - Confidence threshold (Learn Block #1)

Bat_siz - Batch size (Learn Block #1)

Reg_typ - Regularizer type (Learn Block #1)

Rcms - Random crop min scale (Learn Block #1)

Rcms_RcmsLB1 - Random crop max scale (Learn Block #1)

Rcmar - Random crop min aspect ratio (Learn Block #1)

Rcmar_RcmarLB1 - Random crop max aspect ratio (Learn Block #1)

Zoms - Zoom out min scale (Learn Block #1)

Zoms_ZomsLB1 - Zoom out max scale (Learn Block #1)

Bri - Brightness (Learn Block #1)

Con - Contrast (Learn Block #1)

Sat - Saturation (Learn Block #1)

Hue - Hue (Learn Block #1)

Ran_fli - Random flip (Learn Block #1)

Fre_blo - Freeze blocks (Learn Block #1)

Fre_blo_FbLB1 - Freeze blocks (Learn Block #1)

Val_Size - Validation set size (Learn Block #1)

Val_Key - Split train/validation set on metadata key (Learn Block #1)

Mode - Visual / expert mode (Learn Block #1)

CIt - Cluster IoU threshold (Learn Block #1)

Loc_los - Localization loss (Learn Block #1)

Fea_siz - Feature size (Learn Block #1)

Fla - Focal loss alpha (Learn Block #1)

Flg - Focal loss gamma (Learn Block #1)

Nocl - Number of convolutional layers (Learn Block #1)

Accuracy metrics

f32_V_mAP - float32 mAP (validation set)

f32_V_mAP@[IoU=50] - float32 mAP@[IoU=50] (validation set)

f32_V_mAP@[IoU=75] - float32 mAP@[IoU=75] (validation set)

f32_V_mAP@[area=s] - float32 mAP@[area=small] (validation set)

f32_V_mAP@[area=m] - float32 mAP@[area=medium] (validation set)

f32_V_mAP@[area=l] - float32 mAP@[area=large] (validation set)

f32_V_Recall@[max_det=1] - float32 Recall@[max_detections=1] (validation set)

f32_V_Recall@[max_det=10] - float32 Recall@[max_detections=10] (validation set)

f32_V_Recall@[max_det=100] - float32 Recall@[max_detections=100] (validation set)

f32_V_Recall@[area=s] - float32 Recall@[area=small] (validation set)

f32_V_Recall@[area=m] - float32 Recall@[area=medium] (validation set)

f32_V_Recall@[area=l] - float32 Recall@[area=large] (validation set)

f32_T_mAP - float32 mAP (test set)

f32_T_mAP@[IoU=50] - float32 mAP@[IoU=50] (test set)

f32_T_mAP@[IoU=75] - float32 mAP@[IoU=75] (test set)

f32_T_mAP@[area=s] - float32 mAP@[area=small] (test set)

f32_T_mAP@[area=m] - float32 mAP@[area=medium] (test set)

f32_T_mAP@[area=l] - float32 mAP@[area=large] (test set)

f32_T_Recall@[max_det=1] - float32 Recall@[max_detections=1] (test set)

f32_T_Recall@[max_det=10] - float32 Recall@[max_detections=10] (test set)

f32_T_Recall@[max_det=100] - float32 Recall@[max_detections=100] (test set)

f32_T_Recall@[area=s] - float32 Recall@[area=small] (test set)

f32_T_Recall@[area=m] - float32 Recall@[area=medium] (test set)

f32_T_Recall@[area=l] - float32 Recall@[area=large] (test set)

i8_V_mAP - int8 mAP (validation set)

i8_V_mAP@[IoU=50] - int8 mAP@[IoU=50] (validation set)

i8_V_mAP@[IoU=75] - int8 mAP@[IoU=75] (validation set)

i8_V_mAP@[area=s] - int8 mAP@[area=small] (validation set)

i8_V_mAP@[area=m] - int8 mAP@[area=medium] (validation set)

i8_V_mAP@[area=l] - int8 mAP@[area=large] (validation set)

i8_V_Recall@[max_det=1] - int8 Recall@[max_detections=1] (validation set)

i8_V_Recall@[max_det=10] - int8 Recall@[max_detections=10] (validation set)

i8_V_Recall@[max_det=100] - int8 Recall@[max_detections=100] (validation set)

i8_V_Recall@[area=s] - int8 Recall@[area=small] (validation set)

i8_V_Recall@[area=m] - int8 Recall@[area=medium] (validation set)

i8_V_Recall@[area=l] - int8 Recall@[area=large] (validation set)

Target device

Define your target device requirements to inform model optimizations and performance calculations. No device yet? Use the default settings which you can change at any time.

Target device

Processor family

Clock rate

| MHz

Max

Custom device name

Application budget

Specify the available RAM and ROM for the model's operation, along with the maximum allowed latency for your specific application. Not sure yet? Start with the defaults and modify them later on.

RAM

| KB

Max

ROM

| KB

Max

Latency

| ms

Max

Experiments

350 epoch TAO MBv2 0.25 SSD

Image data #1 (Not cleaned dataset), Image, NVIDIA TAO RetinaNet #1 (Primary)

Image data #1 (Not cleaned dataset), Image, NVIDIA TAO RetinaNet #2 (200 epochs)

Image data #1 (Not cleaned dataset), Image, NVIDIA TAO RetinaNet #3 (350 epochs TAO MBv2 0.25 RetinaNet)

MBv2 RetinaNet TAO 160x160