Diego Almeida / Parcial Public

Experiments (1 / 10)

Name Input DSP Blocks Learn Blocks f32_V_Acc f32_T_Acc i8_V_Acc i8_T_Acc Tr_Proc f32_Latency f32_RAM f32_Flash i8_Latency i8_RAM i8_Flash

96×96 Image MobileNetV2 96x96 0.35 74.4% - 62.5% - CPU1581 ms.893.7K2.0M1796 ms.334.7K702.2K