Tea-or-Chocolate - Impulses

Impulses (1 / 3)

Name	tags	Input	DSP Blocks	Learn Blocks	f32_V_Acc	f32_T_Acc	i8_V_Acc	i8_T_Acc	f32_Latency	f32_RAM	f32_Flash	i8_Latency	i8_RAM	i8_Flash
Impulse #1		5,000ms.	Raw data	NN Classifier	100.0%	100.0%	100.0%	100.0%	3 ms.	5.0K	36.2K	1 ms.	4.3K	35.4K	View impulse

Impulse information

Key metrics

f32_V_Acc - Accuracy (float32, validation set)

f32_T_Acc - Accuracy (float32, test set)

i8_V_Acc - Accuracy (int8, validation set)

i8_T_Acc - Accuracy (int8, test set)

f32_Latency - float32 Latency for the complete impulse.

f32_RAM - float32 RAM for the complete impulse.

f32_Flash - float32 Flash for the complete impulse.

i8_Latency - int8 Latency for the complete impulse.

i8_RAM - int8 RAM for the complete impulse.

i8_Flash - int8 Flash for the complete impulse.

Input block config

Win_Size - Window size

Win_Incr - Window increase

Freq - Frequency

Processing block config

Sca_axe - Scaling > Scale axes (Processing Block #1)

Learn block config

Model - ML Model architecture (Learn Block #1)

Tc - Training cycles (Learn Block #1)

Lr - Learning rate (Learn Block #1)

Lo - Use learned optimizer? (Learn Block #1)

Acw - Auto-weight classes (Learn Block #1)

Data_Aug - Data augmentation (Learn Block #1)

Val_Size - Validation set size (Learn Block #1)

Mode - Visual / expert mode (Learn Block #1)

Accuracy metrics

No columns

Target device

Define your target device requirements to inform model optimizations and performance calculations. No device yet? Use the default settings which you can change at any time.

Target device

Processor family

Clock rate

| MHz

Max

Custom device name

Application budget

Specify the available RAM and ROM for the model's operation, along with the maximum allowed latency for your specific application. Not sure yet? Start with the defaults and modify them later on.

RAM

| KB

Max

ROM

| KB

Max

Latency

| ms

Max

Impulses (1 / 3)

Impulse #1