Rob / stage 2 classify speed limit Public

Experiments (1 / 10)

Name Input DSP Blocks Learn Blocks f32_V_Acc f32_T_Acc i8_V_Acc i8_T_Acc f32_Latency f32_Flash i8_Latency i8_Flash

160×160 Image MobileNetV2 96x96 0.35 100.0% 93.5% 93.3% 80.6% 41 ms.1.9M16 ms.650.3K